A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies
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چکیده
A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies Ronaldo Gonçalves, Eduard Ayguadé, Mateo Valero, Philippe Navaux 1 Departamento de Informática, Universidade Estadual de Maringá Avenida Colombo 5790, Maringá, Brazil {[email protected]} 2 Departament d’Arquitectura de Computadors, Universitat Politècnica de Catalunya Jordi Girona 1-3, Barcelona, Spain {eduard, [email protected]} 3 Instituto de Informática, Universidade Federal do Rio Grande do Sul Avenida Bento Gonçalves 9500, Porto Alegre, Brazil {[email protected]}
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تاریخ انتشار 2000